Signal processing apparatus for use with a digital video tape recorder

ABSTRACT

In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such that a circuit for obtaining timing necessary for signal processing is added at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.

DESCRIPTION

1. Technical Field

The present invention relates to a signal processing apparatus, and moreparticularly to an improvement of recording or reproducing apparatus fora digital video tape recorder (D-VTR) for discrete cosine transforming(DCT) video signal in order to compress amount of information thereofand recording it.

2. Background Art

Heretofore, as this type of D-VTR, there is one shown in FIG. 1. In FIG.1, 1 generally denotes the D-VTR. A digital video signal S1 (FIG. 2(B))input from a predetermined video signal generating unit is input to aDCT shuffling circuit 2. The DCT shuffling circuit 2 has a DCT addresscircuit 3 in association therewith, a vertical synchronizing signalS_(V) (FIG. 2(A)) is input to the DCT address circuit 3.

Accordingly, the DCT shuffling circuit 2 divides the digital videosignal S1 into DCT blocks of 8 columns×4 rows for each one field byshuffle address generated by the DCT address circuit 3 on the basis ofthe vertical synchronizing signal S_(V). The DCT shuffling circuit 2collects 10 blocks of the DCT blocks from their respective positionsdiscretely located from each other within a screen to generate shuffledata S2 (FIG. 2(C)), and outputs the shuffle data S2 to the followingDCT conversion circuit 4.

Here, the DCT shuffling circuit 2 performs shuffling processing by eachone field. Thereby, the shuffle data S2 output from the DCT shufflingcircuit 2 is supplied to the DCT conversion circuit 4 at a timingdelayed by one field time period T2 from the digital video signal S1 asshown in FIG. 2(C).

The DCT conversion circuit 4 performs discrete cosine transform to dataof each DCT block and supplies DCT data S3 to a quantization delaycircuit 5 and a quantization level detecting circuit 6. The quantizationlevel detecting circuit 6 detects a quantization level (quantizationwidth) for achieving a target compression rate for the DCT data S3.Since, at this time, about ten-block time period is required as thesignal processing time in the quantization level detecting circuit 6,the quantization delay circuit 5 delays the DCT data S3 by the signalprocessing time, and supplies it to a quantization circuit 7 as aquantization delay output data S5. Accordingly, the quantization delayoutput data S5 is input to the quantization circuit 7 at the same timingas quantization level data S4 which is output from the quantizationlevel detecting circuit 6 at a time point t3 delayed by a 10-block timeperiod T3 from the shuffle data S2 as shown in FIG. 2(D).

The quantization circuit 7 quantizes the quantization delay output dataS5 supplied from the quantization delay circuit 5 based on thequantization level data S4 supplied from the quantization leveldetecting circuit 6 in order to compress amount of information thereof.At this time, the quantization circuit 7 detects a maximum value, aminimum value, and a mean value etc., of quantization level within onefield, on the basis of a period signal for each one field obtained fromthe vertical synchronizing signal S_(V) at a vertical counter 8 providedin association therewith, and outputs the result as detection data S6 toa quantization monitor (not shown) to monitor the state of compressionof data at the quantization circuit 7.

Further, quantization data S7 obtained from the quantization circuit 7is supplied to a variable-length coding circuit 9. The variable-lengthcoding circuit 9 performs variable-length coding to the quantizationdata S7 to generate variable-length coding data S9 having a block lengthprescribed in a format, and outputs it to an error correcting outercoding circuit 11.

The error correcting outer coding circuit 11 generates an errorcorrecting outer code for correcting an error occurred in the manner ofa burst, on the basis of a timing obtained from the verticalsynchronizing signal S_(V) at a parity timing circuit 12 which isprovided in association therewith, and the result is added to thevariable-length coding data S9 and is output to a track shufflingcircuit 13.

The track shuffling circuit 13 generates track shuffle data S13 byrecording the data into an order suitable for the track pattern on amagnetic tape, in accordance with shuffle address obtained from thevertical synchronizing signal S_(V) at a track address circuit 14 whichis provided in association therewith.

The track shuffle data S13 is supplied to an error correcting innercoding circuit 15. The error correcting inner coding circuit 15generates an error correcting inner code for correcting random error andadds to the track shuffle data S13. An ID counter 16 which is providedin association with the error correcting inner coding circuit 15,obtains a block number obtained from the vertical synchronizing signalS_(V) and the color field signal S_(C), and color field informationcorresponding to a time period when the phase shift of carrier resultingfrom phase shifts by each scanning line completes a cycle.

The error correcting inner coding circuit 15 adds the block number andthe color field information to the track shuffle data S13 as IDinformation, and outputs the result to a recording circuit 17 asrecording data S12. The recording circuit 17 converts the recording dataS12 from an 8 bit! parallel form to 1 bit! serial form and effectschannel coding suitable for magnetic recording, and records on amagnetic tape 19 by means of a magnetic head 18 provided on a rotarydrum.

Here, since the track shuffling circuit 13 performs re-orderingprocessing of data by each 1/3 field, the recording data S12 obtained onthe basis of the track shuffle data S13 is output from the errorcorrecting inner coding circuit 15 at a time point t4 delayed by 1/3field period T4 from quantization delay output data S5 output from thequantization delay circuit 5 as shown in FIG. 2(E).

Here, in the recording data S12 in the D-VTR 1, a synchronizing patternis added to the beginning of a data block as a delimiter for the blockand a delimiter for restoring data recorded in 1 bit! serial form on themagnetic tape into the original 8 bit! parallel form.

Further, a block number for indicating the sequential order of each datablock is added as ID information at the error correcting inner codingcircuit 15, so that an image is reproduced even when data blocks are notcontinuously reproduced as the reproducing head helically scans aplurality of tracks in double-speed reproducing etc. Furthermore, colorfield information is also added as ID information at the errorcorrecting inner coding circuit 15.

Further, video data generated through the above DCT shuffling circuit 2to the error correcting inner coding circuit 15 is recorded subsequentlyto the ID information. At the beginning of the video data, thequantization level information in data compression is added at thequantization circuit 7 in accordance with the quantization level dataS4. Furthermore, an inner parity data for correcting a random error isadded at the error correcting inner coding circuit 15.

In the D-VTR 1 of such construction, data is output with a delay of thetime necessary for the signal processing at each signal processingcircuit. For example, at the DCT shuffling circuit 2, data is outputwith a delay corresponding to one field time period T2 (FIG. 2(C)), andat the quantization delay circuit 5, data is delayed by 10-block timeperiod T3 (FIG. 2(D)). Further, at the DCT conversion circuit 4, thequantization circuit 7, and the variable-length coding circuit 9, datais delayed by about one block time period respectively, and at the trackshuffling circuit 13, data is delayed by 1/3 field time period T4 (FIG.2(E)).

Accordingly, at the timing circuits of the vertical counter 8, theparity timing circuit 12, the track address circuit 14, and the IDcounter 16, timing signals must be generated with their phase conformingto their respective delay time from the vertical synchronizing signalS_(V).

Further, while the color field information is input at the same timingas the digital video signal S1, data (track shuffle data S13) input tothe error correcting inner coding circuit 15 to which the color fieldinformation is to be added as ID information is delayed by about 1.4field from the input point t1 (FIGS. 2(A) to 2(E)) of the digital videosignal S1. Accordingly, a latch circuit for reading the color fieldinformation with a delay corresponding to such delay time is necessaryat the ID counter 16, resulting in a problem of complicating theconstruction.

Further, all of these delay phases occur as an accumulation ofprocessing time in the signal processing circuits up to the previousstage of that point and, when processing time of a signal processingcircuit is changed in its development process, timing of all the signalprocessing circuits after the changed signal processing circuit must becorrected in accordance with such changed time period.

DISCLOSURE OF INVENTION

Considering the above points, the present invention provides a signalprocessing apparatus such that, data to be output with a delay at eachsignal processing circuit can securely be processed and deliveredirrespective of delay time of the data due to the signal processing timeof the respective signal processing circuit.

To solve such problems according to the present invention, a signalprocessing apparatus having a plurality of signal processing circuitswhich are sequentially connected so as to make a desired data into apredetermined unit and sequentially perform signal processing, at leastone of which performs a predetermined signal processing to the desireddata at the timing determined on the basis of a processing timing of theanother signal processing circuits, wherein at least one of signalprocessing circuits outputs the desired data with adding timing dataindicating the processing timing. The another signal processing circuitsset the timing of signal processing for the desired data on the basis ofthe timing data.

Further, in the present invention, a signal processing apparatus havinga plurality of signal processing circuits which are sequentiallyconnected so as to make video data into a predetermined unit andsequentially perform signal processing, at least one of which performspredetermined signal processing to the video data at the timingdetermined on the basis of a processing timing of the another signalprocessing circuits, wherein at least one of signal processing circuitsoutputs the video data with adding timing data indicating the processingtiming. The another signal processing circuits set the timing of signalprocessing for the video data on the basis of the timing data.

Further, in the present invention, a signal processing apparatus 20 fordigital video signal for performing a predetermined signal processingfor digital video signal S1, comprising: a block shuffling circuit 21for making input digital video signal S1 into a predetermined unit inorder to perform a block conversion coding and shuffling it to obtainshuffle data S21, and then for outputting the shuffle data S21 withadding a block number information D_(BL) and a color field informationD_(FI) of the digital video signal S1 as header data; a block conversioncoding circuit 23 receiving the output of the block shuffling circuit 21for performing block conversion coding for the shuffle data S21 andobtain coding data S22, and for outputting the coded data S22 withadding the header data; a quantization circuit 25 receiving the outputof the block conversion coding circuit 23 for quantizing the coding dataS22 and obtain quantized data S25, and for outputting the quantized dataS25 with adding the header data to which quantization level informationD_(Q) in quantizing is added to the quantized data S25; avariable-length coding circuit 26 receiving the output of thequantization circuit 25 for processing variable-length coding to thequantized data S25 to obtain variable-length coded data S26, and foroutputting the variable-length coded data S26 with adding the headerdata; an error correcting outer coding circuit 27 receiving the outputof the variable-length coding circuit 26 for generating error correctingcoding data in accordance with the block number information D_(BL), andfor outputting the error correcting coding data with adding the outputof the variable-length coding circuit 26; a shuffling circuit 28receiving the output of the error correcting outer coding circuit 27 forshuffling the variable-length coded data in accordance with the blocknumber information D_(BL), and for outputting the shuffle data withadding the header data to obtain shuffle data S28, and for outputtingthe shuffle data S28 with adding the header data; and an errorcorrecting inner coding circuit 29 receiving the output of the shufflingcircuit 28 for generating an error correcting inner code data inaccordance with the block number information D_(BL) and the color fieldinformation D_(FI), and for outputting the error correcting inner codedata with adding the output of the shuffling circuit 28.

When the desired data S1 is output sequentially through each of thesignal processing circuits 21 to 29, timing data D_(FI), D_(BL), and/orD_(Q) are/is added to the data S1 and processing at each signalprocessing circuit 21 to 29 is performed at a timing based on the timingdata D_(FI), D_(BL), and/or D_(Q), so that the data S1 can be deliveredbetween the signal processing circuits 21 to 29 without regard toprocessing time in the respective signal processing circuits 21 to 29.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the construction of a conventionalrecording and/or reproducing apparatus;

FIGS. 2(A) to 2(E) are signal waveform diagrams explaining delayed stateof data due to the signal processing;

FIG. 3 is a schematic diagram explaining a recording format in recordingand/or reproducing by a recording and/or reproducing apparatus accordingto the present invention;

FIG. 4 is a schematic diagram explaining the structure of the syncblocks;

FIGS. 5(A) and 5(B) are schematic diagrams explaining contents recordedin the identification pattern of the sync blocks;

FIG. 6 is a block diagram showing the construction of an embodiment ofrecording and/or reproducing apparatus according to the presentinvention; and

FIGS. 7(A) to 7(C) are schematic diagrams explaining data arrangementbeing used in the recording and/or reproducing apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described in detail, withthe accompanying drawings:

FIG. 3 shows a recording format on a magnetic tape which is recorded bya D-VTR according to the present invention. Digital video signal anddigital audio signal for one field are made into a predetermined unitand recorded in the area of six helical recording tracks. The sixrecording tracks are segmented by two recording tracks and at each ofwhich the segment number 1, 2, 3 are sequentially allocated from thehead of one field.

Further, the track number 0 or 1 is allocated to the two recordingtracks of respective segment. In one recording track, a preamble, videodata of 126 sync blocks, audio data of 6 sync blocks×4 channels, andanother video data of 126 sync blocks are sequentially recorded.

Here, as shown in FIG. 4, each sync block is 180-byte length, in whichat the beginning 2 bytes, a synchronization pattern SYNC is recorded, atthe succeeding 2 bytes, an identification pattern ID is recorded, at thesucceeding 162 bytes, compressed video data, audio data, or these errorcorrecting outer code parity is recorded as a recording data DATA, andat the end 14 bytes, an error correcting inner code parity IP of theidentification pattern ID or recording data DATA is recorded.

Practically, in the synchronization pattern SYNC, for example, the value"2ED3(H)" is recorded as a fixed pattern. At the beginning one byte,corresponding numbers of sync block are recorded as the identificationpattern ID in the sequence of FIG. 5(A). Further, at the succeeding onebyte, flag information indicating the property of corresponding syncblock is recorded as an identification pattern ID by sector numbers asshown in FIG. 5(B).

That is, when being the value "1", bit 0 of the LSB in this byteindicates the sector of video data, and when being the value "0", whichis an identification flag indicating the sector of audio data. At thebit 1, the value "0" or "1" is recorded as a track number in the abovesegment number. At the bits 2 and 3, the value "1", "2", or "3" of theabove segment number is recorded in 2 bits. At the bits 4, 5, and 6, acolor field information is recorded. The bit 7 of the MSB indicates aformat of the digital video data, and when being component video data,the value "1" is recorded, and when being composite video data, thevalue "0" is recorded.

In the D-VTR 20 shown in FIG. 6, the corresponding part to FIG. 1 isdenoted by the same numerals. A DCT address circuit 22 generates ashuffle address on the basis of the vertical synchronization signalS_(V), and a DCT shuffling circuit 21 shuffles digital video signal S1in accordance with the shuffle address to generate shuffle data S21, andsupplies it to a DCT circuit 23.

At this time, as shown in FIG. 7(A), the DCT shuffling circuit 21 adds ablock number D_(BL) generated by the DCT address circuit 22 and a colorfield information D_(FI) to DCT block data D_(SH) as header information.Here, the block number D_(BL) corresponds to the total of the sync blocknumber of the first byte in the identification pattern ID which has beendescribed accompanying with FIGS. 4 and 5(A) and 5(B), the dataidentification flag, the segment number, and the track number of thebits 0 to 3 of the second byte, and the color field information D_(FI)corresponds to the color field information of the bits 4 to 6 of thesecond byte.

The DCT transformation circuit 23 performs discrete cosinetransformation for respective DCT block data D_(SH) on the basis of theblock number D_(BL) and color field information D_(FI), and supplies theresult as DCT data S22 to a quantization level delay circuit 24. Thequantization level delay circuit 24 detects a quantization level fordetermining a quantized width at the following quantization circuit 25while delaying the DCT data S22, and as shown in FIG. 7(B), outputs theDCT data D_(DCT) to a quantization circuit 25 as quantization leveldelay output data S23 with thus detected quantization level informationD_(Q) added as a header information.

The quantization circuit 25 quantizes the DCT data D_(DCT) on the basisof the quantization level information D_(Q) added as a headerinformation in order to compress. At this time, the head and end of thefield are investigated by the block number D_(BL) added as a headerinformation to calculate the mean value of the quantization levels,etc., the calculated result S24 is output to a quantization monitor (notshown), so that the compressed state can be monitored.

Further, in the quantization circuit 25, the compression-processedquantized data S25 is supplied to a variable-length coding circuit 26 tobe variable-length coded. Thus obtained variable-length coded data S26is supplied to an error correcting outer coding circuit 27.

The error correcting outer coding circuit 27 generates a parity timingfrom the block number D_(BL) (FIGS. 7(A) and 7(B)) which is inassociation with the variable-length coded data S26 as a headerinformation to generate an error correcting outer code. Further, thefollowing track shuffling circuit 28 also generates a shuffle addressfrom the block number D_(BL) (FIGS. 7(A) and 7(B)) which is inassociation with the variable-length coded data S26 in order to re-orderthe data, and sends it to the following error correcting inner codingcircuit 29 as track shuffle data S28.

The error correcting inner coding circuit 29 generates an errorcorrecting inner code, and adds the synchronization pattern SYNC togenerate recording data S12 shown in FIG. 7(C). The recording data S12is recorded on a magnetic tape 19 through the following recordingcircuit 30 and magnetic head 18. At this time, in the error correctinginner coding circuit 19, since the block number D_(BL) and fieldinformation D_(FI) which are necessary as ID information, are previouslyadded to the data as header information, it is unnecessary to add thoseagain.

Further, in the reproducing system, reproduced data S31 which isreproduced through a reproducing head 31 and reproducing circuit 32 isinput to a correcting circuit 33 to be correction-processed by using theerror correcting inner code recorded with the recording data, and isoutput to a de-shuffling circuit 34. The de-shuffling circuit 34de-shuffles the reproduced data re-ordered to the sequence correspondingto the track pattern on the magnetic tape into the original sequence,and outputs it to the following correcting circuit 35 as de-shuffle dataS34.

The correcting circuit 35 corrects an error in the manner of burst ofthe de-shuffle data S34 and outputs it to the following variable-lengthdecoding circuit 36. The variable-length decoding circuit 36 obtainsvariable-length decoded data S35 from the de-shuffle data S34 andoutputs it to an inverse-quantization circuit 37 to performinverse-quantization processing. The inverse-quantization circuit 37outputs thus obtained inverse-quantized data S37 to an IDCT circuit toperform inverse-transform processing for discrete cosine transformationat the DCT transforming circuit 23 described above. The IDCT circuitoutputs thus obtained IDCT data S38 to the following de-shufflingcircuit 39 to re-order the DCT-blocked data in the sequence of scanning,and outputs it as reproducing digital video signal S39.

In the above configuration, the D-VTR 20 adds the block number D_(BL)and field number D_(FI) to the digital video signal S1 as headerinformation at the DCT shuffling circuit 21, and further adds thequantization level information D_(Q) as a header information at thequantization level delay circuit 24. By using the header information,information necessary for the signal processing can be obtained fromonly input data at each signal processing circuit, further theinformation is input at the same timing as the processing data.

The header information is used as a timing information at each signalprocessing circuit, and signal processing is performed in accordancewith the timing of the above header information, so that in each signalprocessing circuit, signal processing can be performed at the securelytiming without regard to the processing delay time of signal processingcircuits connected to the previous stage or latter stage. Therefore, ineach signal processing circuit, a counter circuit for generating timingin respective signal processing, a latch circuit for timing phases bydelaying the information, etc. can be omitted.

Further, the color field information D_(FI) is added as a headerinformation, so that the color field information D_(FI) is delayed withthe data at each signal processing circuit and transmitted to the lastrecording data S12. Further, also the quantization level informationD_(Q) detected at the quantization level delay circuit 24 is added tothe data as a header information, so that at the quantization circuit 25of next stage, the quantizing operation can be executed by investigatinga quantization level from the header information.

In such a manner, new information is added as a header information atthe signal processing circuit of halfway, so that the signal connectionbetween complicated circuits such as the conventional D-VTR 1 describedabove with FIG. 1, in which the quantization level detecting data S4 isoutput from the quantization level detecting circuit 6 to thequantization circuit 7 separated from the quantization delay output dataS5, can be reduced, and transmitting the data to a latter stage of thesignal processing circuit without regard to delay time at each signalprocessing circuit.

As the above configuration, when performing signal processing at eachsignal processing circuit, the timing necessary for respective signalprocessing is added for the data to be transmitted, as a headerinformation, so that each signal processing circuit can be avoided to becomplicated structure such that a circuit for obtaining the timingnecessary for the signal processing is added at the respective signalprocessing circuits.

Further, in each signal processing circuit, the signal processing can beperformed without generating a timing necessary for the signalprocessing at the respective signal processing circuits, so that thesignal processing circuit can be developed Without regard to delay timeat each signal processing circuit. Therefore, even if processing time ofeach signal processing circuit is changed in its development process,the signal processing circuit provided to a latter stage of the abovesignal processing circuit may not be changed in accordance with the suchchanged time period, so can be developed more easily.

Note that, in the embodiment described above, it has been described thecase where the present invention is being applied to a D-VTR. However,the present invention is not only limited to this, but is widelyapplicable to a signal processing apparatus such that data istransmitted via a plurality of signal processing circuits.

INDUSTRIAL APPLICABILITY

The present invention is being suitable to apply to a signal processingapparatus, for example, being a recording or reproducing apparatus fordigital video tape recorder (DVTR) for discrete cosine transformingvideo signal in order to compress amount of information thereof andrecord.

I claim:
 1. A signal processing apparatus for digital video signal forperforming a predetermined signal processing for digital video signal,comprising:a block shuffling circuit for making input digital videosignal into a predetermined unit in order to perform a block conversioncoding and shuffle it to obtain a shuffle data, and then for outputtingsaid shuffle data with adding a block number information and color fieldinformation of said digital video signal as header data; a blockconversion coding circuit receiving the output of the block shufflingcircuit for performing block conversion coding for said shuffle data toobtain coded data, and for outputting said coded data with adding saidheader data; a quantization circuit receiving the output of the blockconversion coding circuit for quantizing said coded data to obtainquantized data, and for outputting said quantized data with adding saidheader data to which quantization level information in quantizing isadded; a variable-length coding circuit receiving the output of thequantization circuit for processing variable-length coding to saidquantized data to obtain variable-length coded data, and for outputtingsaid variable-length coded data with adding said header data; and anerror correcting outer coding circuit receiving the output of thevariable-length coding circuit for generating error correcting codingdata in accordance with said block number information, and foroutputting said error correcting coding data with adding the output ofsaid variable-length coding circuit.
 2. The signal processing apparatusaccording to claim 1 further comprising, a shuffling circuit receivingthe output of said error correcting outer coding circuit for shufflingsaid variable-length coded data in accordance with said block numberinformation to obtain shuffle data, and for outputting said shuffle datawith adding said header data.
 3. The signal processing apparatusaccording to claim 2 further comprising, an error correcting innercoding circuit receiving the output of said shuffling circuit forgenerating an error correcting inner code data in accordance with saidblock number information and said color field information, and foroutputting said error correcting inner code data with adding the outputof said shuffling circuit.
 4. The signal processing apparatus accordingto claim 1, wherein said block conversion coding is performed by amethod of discrete cosine transform.